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Verification of Transaction Level Models of Embedded Systems

dc.creatorYu Lo, Lucky Lochi
dc.date2013-11-19
dc.date.accessioned2016-05-03T15:10:35Z
dc.date.available2016-05-03T15:10:35Z
dc.identifierhttp://revistas.ucr.ac.cr/index.php/ingenieria/article/view/11662
dc.identifier10.15517/ring.v23i2.11662
dc.identifier.urihttps://hdl.handle.net/10669/24554
dc.descriptionAs complexity increases in embedded systems design, there is need for more time for verification purposes. For embedded systems, the only verification that can be done is running test cases, and the number of cases increases exponentially. In order to shorten this verification phase of the design, we propose a methodology to do formal verification of embedded systems. In formal verification no test cases are needed, but an mathematical analysis of the original model and the refined one. We base our tool on the Model Algebra theory of embedded systems, and apply its transformation rules to our models to check for equivalency. We test this transformation rules in various scenarios and prove that it is a promising methodology to improve embedded system design.es-ES
dc.formatapplication/pdf
dc.formattext/html
dc.languagespa
dc.publisherUniversidad de Costa Ricaen-US
dc.relationhttp://revistas.ucr.ac.cr/index.php/ingenieria/article/view/11662/15657
dc.rightsCopyright (c) 2014 Revista Ingenieríaen-US
dc.sourceJournal of Tropical Engineering; Vol 23, No 2 (2013)en-US
dc.sourceRevista Ingeniería; Vol 23, No 2 (2013)es-ES
dc.sourceIngeniería; Vol 23, No 2 (2013)pt-PT
dc.source2215-2652
dc.source1409-2441
dc.titleVerification of Transaction Level Models of Embedded Systemses-ES
dc.typeartículo original


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