Verification of Transaction Level Models of Embedded Systems
Yu Lo, Lucky Lochi
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As complexity increases in embedded systems design, there is need for more time for verification purposes. For embedded systems, the only verification that can be done is running test cases, and the number of cases increases exponentially. In order to shorten this verification phase of the design, we propose a methodology to do formal verification of embedded systems. In formal verification no test cases are needed, but an mathematical analysis of the original model and the refined one. We base our tool on the Model Algebra theory of embedded systems, and apply its transformation rules to our models to check for equivalency. We test this transformation rules in various scenarios and prove that it is a promising methodology to improve embedded system design.